The Ivy Bridge






Starter Kit

Spartan3E Starter Kit

Projects for the Spartan3E

Xilinx have shipped over 20 million Spartan-3 family devices. The Spartan-3E is optimised for applications where logic densities matter more than I/O count. It is ideal for logic integration, DSP co-processing and embedded control, requiring significant processing and narrow or few interfaces.

The Spartan3E Starter Kit is a very good starting point for exploring all the features. At Ivysim we are in the process of documenting some projects that we built to better understand what the Spartan3E can do. If you need a consultant to help you develop a Spartan3E design or you would like us to undertake the whole FPGA development then call. If FPGA work is a small part of your engineering development effort then it might make a lot of sense to out-source this to a specialist.

Below you will find some Spartan-3E projects.

Step One: UCF and Toplevel VHDL File

At Ivysim we don't like to repeat work. Reuse is what we do best and we create many Tcl and Perl utilities to help us do that. Editing the User Constraints File (UCF) for pin placements and IO standards is necessary at project start. However, it is fiddly, especially for new projects. Here is a utility that does all the fiddling for you.

UCF and VHDL Entity Generator

Step Two: Quick ISE

You want a rapid flow from VHDL to bit file and download. You want it to be simple. Try Quick ISE. It is simpler and faster than the ISE graphical user interface and is perfectly suited to many Spartan3E projects (and other Xilinx FPGAs).

Quick ISE

Picoblaze Verification

This is an example project showing the power and simplicity of the free Picoblaze soft-core. It shows some smart verification techniques to productively model both hardware and software in ModelSim.

Picoblaze Project

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