UCF and Toplevel VHDL Entity
This simple tool greatly simplifies starting new projects. It generates UCF and VHDL files for the Spartan3E Starter Kit. It helps later when you need to change toplevel ports too.
Xilinx designs need UCFs (user constraints files) to provide pin assignment and IO standard information. Global timing constraints (as a minimum) should be provided too.
This tool is specific to the Spartan3E Starter Kit, it knows which FPGA pins are connected to which peripherals. It also knows what pullup and pulldown resistors switch inputs need, etc. If you would like Ivysim to create a similar tool for another board then call us.
Port names with checkboxes are displayed for you to select which pins you want to use. You don't have to keep the port names in your design. Ports will be renamed inside the toplevel VHDL wrapper.
How It Works
Download the Windows or Linux version. Run the tool from the directory where you would like the UCF and VHDL files to be saved. Old files are overwritten without any warning so make sure you are not about to overwrite other constraints you may have added from, say, the Xilinx Timing Constraints Editor.
Port names and displayed comments are derived from the reference UCF provided with the Starter Kit User Guide. Select the ports that you need in the design. It is best to standardise on the names already given. Otherwise, if you have a good reason for deviating, make changes to names in the entry fields.
Choose Save from the File menu (Ctrl-S). Two files are generated: spartan3e.ucf and spartan3e.vhd.
The UCF contains the User Guide reference UCF with location constraints for unused pins commented out. The VHDL file contains two entities: spartan3e and spartan3e_wrapper. The toplevel entity for your project will be spartan3e_wrapper. This retains all the original pin names and its architecture patches them into the changed names of the entity spartan3e. If you didn't change any names then you could ignore spartan3e_wrapper and simply make spartan3e your toplevel entity.
Top Tip: Writing the toplevel architecture for entity spartan3e in a separate file will eliminate the risk that you overwrite it later if you inadvertently regenerate spartan3e.vhd.
Toplevel Port Changes
If you need to add, remove or rename top level ports then run the tool again in the same directory as spartan3e.vhd. You may wish to copy spartan3e.vhd to a temporary directory first. The tool will read in the ports and names that you are already using. Then you can add, remove and rename ports before saving again. The VHD and UCF files are overwritten without warning.
This is free software. There is no warranty. Licence details can be found in Help menu. We hope you find it useful for your Spartan3E projects.
Room For Improvement
This tool was created in about 30 minutes. It is for engineering applications and might save 20-30 minutes per project. We have kept it simple with, for example, no warnings for overwriting existing files. We are open to suggestions for improvement.
If you need tools for similar applications then we could write them for you. Paying for a couple of hours of consultancy time may save you days of project time. It can be astonishing how much time a simple software tool can save. Any text processing activity can be automated. If you are not sure then call and we'll talk about it.
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